1. Field of the Invention
The present invention relates to a multi-input differential amplifier, and more specifically, to a multi-input differential amplifier capable of performing dynamic transconductance compensation to enhance output voltage accuracy and increase input voltage interpolation range.
2. Description of the Prior Art
Generally, to reduce chip area, a multi-bit output buffer of a driving chip usually utilizes multi-input-pair interpolation amplifiers, which operate by inputting input voltage values with different weighting, and then generating a combined output voltage via interpolation.
For example, please refer to FIG. 1, which is a schematic diagram of a conventional eight-to-one digital analog convertor (DAC) 10. As shown in FIG. 1, the eight-to-one DAC 10 selects a suitable voltage to output from eight input voltages, according to a received 3-bit digital analog conversion code DACC. However, this architecture requires 2^3−1 devices for selection, and is therefore costly in terms of chip area.
To reduce chip area, the prior art adopts the multiple output voltage architecture, then performs interpolation to obtain the intended output voltage. Please refer to FIG. 2A and FIG. 2B; FIG. 2A is a schematic diagram of a conventional eight-to-four DAC 20, and FIG. 2B is a schematic diagram of a conventional multi-input differential amplifier 22 for the eight-to-four DAC 20 shown in FIG. 2A. As shown in FIG. 2A and FIG. 2B, the eight-to-four DAC 20 can output a permutation of voltage levels VL or VH (level VL is lower than level VH) as input voltages V1-V4 of the multi-input differential amplifier 22 according to the 3-bit digital analog conversion code DACC, to produce a suitable voltage level. In other words, the eight-to-four DAC 20 can generate at most eight combinations of the input voltages V1-V4 to the multi-input differential amplifier 22 to perform interpolation according to the 3-bit digital analog conversion code DACC, and therefore does not require eight specific input voltages for selection, thus allowing a smaller chip area than the eight-to-one DAC 10.
To implement interpolation functionality, the multi-input differential amplifier 22 is usually arranged in a unit gain buffer architecture (having an output voltage Vo fed to a negative input terminal in negative feedback), and thus it is possible to obtain a suitable output voltage Vo via performing interpolation on the input voltages V1-V4. In other words, it is possible to generate a suitable output voltage Vo via inputting the input voltages V1-V4 with different weightings of the levels VL and VH to the multi-input differential amplifier 22 for interpolation.
However, the output voltage Vo of differential input pairs of the conventional multi-input differential amplifier 22 often deviates from a designated interpolation value, thus limiting a range of possible interpolated values between levels VL, VH for the input voltages V1-V4 of the multi-input differential amplifier 22.